智能系统学报2012，Vol.7Issue(4)：302-306,5.DOI:10.3969/j.issn.1673-4785.201202002
基于FPGA的全流水双精度浮点矩阵乘法器设计
Design of an FPGA-based double-precision floating-point matrix multiplier with pipeline architecture
摘要
Abstract
Many application areas, such as digital communication and image processing, make extensive use of ma-trix multiplication operations, and the computational performance of this operation is critical for the whole system. A parallel double-precision floating-point matrix multiplier with pipeline architecture was designed to improve the computational performance. The design was implemented in a Xilinx Virtex-5 LX155 field programmable gate array ( FPGA). Up to 10 processing elements were integrated in a single FPGA device, and they were arranged as an ar-ray to achieve parallel computation. The processing elements employed pipelined architecture to increase the speed, and C-slow retiming was applied to solve the data-related conflicts issues on the loop pipeline. The post-Route sim-ulation results show that the peak performance of the matrix multiplier can achieve 5 000 MFLOPS. In addition, the matrix multiplication experiments with differenl dimensions were carried out, and the results confirm that the design achieved high computational performance.关键词
矩阵乘法/现场可编程门阵列(FPGA)/环路流水线/C-slow时序重排技术/乘法器设计Key words
matrix multiplication/FPGA/loop pipeline/C-slow retiming/multiplia design分类
信息技术与安全科学引用本文复制引用
刘沛华,鲁华祥,龚国良,刘文鹏..基于FPGA的全流水双精度浮点矩阵乘法器设计[J].智能系统学报,2012,7(4):302-306,5.基金项目
国家自然科学基金资助项目(61076014) （61076014）
江苏省高校自然科学基金资助项目(10KJA510042) （10KJA510042）
先导项目(XDA06020700). （XDA06020700）
