首页|期刊导航|电子科技学刊|A Strong Anti-Jamming Algorithm Based on FPGA for Estimating Loop Delay in Digital Predistortion System

A Strong Anti-Jamming Algorithm Based on FPGA for Estimating Loop Delay in Digital Predistortion System

Feng-Jun Li Jing-Fu Bao Hong-Yun Huang Shao-Chun Jin

电子科技学刊2012，Vol.10Issue(4)：358-362,5.

电子科技学刊2012，Vol.10Issue(4)：358-362,5.DOI:10.3969/j.issn.1674-862X.2012.04.012

A Strong Anti-Jamming Algorithm Based on FPGA for Estimating Loop Delay in Digital Predistortion System

Feng-Jun Li ¹Jing-Fu Bao ¹Hong-Yun Huang ¹Shao-Chun Jin¹

作者信息

1. School of Electronic Engineering, University of Electronic Science and Technology of China, Chengdu 610054, China
折叠

摘要

关键词

Baseband/digital predistortion/linear interpolation/loop delay estimation/power amplifier

Key words

Baseband/digital predistortion/linear interpolation/loop delay estimation/power amplifier

引用本文复制引用

Feng-Jun Li,Jing-Fu Bao,Hong-Yun Huang,Shao-Chun Jin..A Strong Anti-Jamming Algorithm Based on FPGA for Estimating Loop Delay in Digital Predistortion System[J].电子科技学刊,2012,10(4):358-362,5.

基金项目

This work was supported by the Circuit and System Foremost Discipline of Zhejiang Province under Grant No.ZZ050103-11. （）

电子科技学刊

ISSN：1674-862X

访问量0

下载量0

段落导航