计算机工程与科学2013，Vol.35Issue(3)：80-84,5.DOI:10.3969/j.issn.1007-130X.2013.03.013
基于FPGA的AES核设计
Design of AES Core Based on FPGA
摘要
Abstract
AES has its remarkable advantages in security, high performance, high efficiency, ease of use, flexibility, etc. As the demand of computation performance increases, researches on AES's FPGA implementation are paid more attention to. Based on the analysis of AES algorithm, a FPGA based fully pipelined AES model is proposed. In this model, the structure of the ae data block and wheel computation are modified in order to improve the performance of the AES hardcore. The implementation results on Altera EP4CE40F23C6 FPGA show that the proposed AES hardcore can run at 310 MHz with the computation throughput of 9. 92 Gbps at the cost of 6413 LE and 80 M9K.关键词
AES/全流水线/计算加速/FPGAKey words
AES/ fully pipeline computing acceleration/ FPGA分类
信息技术与安全科学引用本文复制引用
韩津生,林家骏,周文锦,叶建武..基于FPGA的AES核设计[J].计算机工程与科学,2013,35(3):80-84,5.基金项目
国家自然科学基金资助项目(60903186) （60903186）
