光通信技术2013，Vol.37Issue(2)：44-46,3.
SDH中E3复用/解复用系统的FPGA实现
Implementation of E3 multiplexing/demultiplexing system in SDH based on FPGA
摘要
Abstract
E3 multiplexing/demultiplexing system in SDH is designed based on FPGA,including HDB3 coding and decoding,code rates adjustment,mapping/demapping,location/delocation,multiplexing/demultiplexing.Then,function simulation,synthesis,layout and timing simulation are conducted through Quartus Ⅱ 9.0 until the functions have been realized,the designed results are verified by the fourth generation of Altera's Cyclone EP4CE115F29C7N.We use SDH analyzer (ANT-5) to test the designed multiplexing/demultiplexing system,measurement time is one week,the tested results show that our designs are correct.关键词
同步数字系列/现场可编程门阵列/E3/复用/解复用Key words
synchronous digital hierarchy (SDH)/ field programmable gate array(FPGA)/ E3/ multiplexing/ demultiplexing分类
信息技术与安全科学引用本文复制引用
胡辽林,刘雪峰..SDH中E3复用/解复用系统的FPGA实现[J].光通信技术,2013,37(2):44-46,3.基金项目
陕西省教育厅科学研究计划(2010JK716)资助. （2010JK716）
