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An ultra-low-power area-efficient non-volatile memory in a 0.18 μ m single-poly CMOS process for passive RFID tags

Jia Xiaoyun Feng Peng Zhang Shengguang Wu Nanjian Zhao Baiqin Liu Su

半导体学报（英文版）2013，Vol.34Issue(8)：94-98,5.

半导体学报（英文版）2013，Vol.34Issue(8)：94-98,5.DOI:10.1088/1674-4926/34/8/085004

An ultra-low-power area-efficient non-volatile memory in a 0.18 μ m single-poly CMOS process for passive RFID tags

Jia Xiaoyun ¹Feng Peng ²Zhang Shengguang ¹Wu Nanjian ¹Zhao Baiqin ²Liu Su¹

作者信息

1. State Key Laboratory for Super Lattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences,Beijing 100083, China
2. Institute of Microelectronics, School of Physical Science and Technology, Lanzhou University, Lanzhou 730000, China
折叠

摘要

关键词

non-volatile memory/ ultra-low-power/ area-efficient/ CMOS/ RFID

Key words

non-volatile memory/ ultra-low-power/ area-efficient/ CMOS/ RFID

引用本文复制引用

Jia Xiaoyun,Feng Peng,Zhang Shengguang,Wu Nanjian,Zhao Baiqin,Liu Su..An ultra-low-power area-efficient non-volatile memory in a 0.18 μ m single-poly CMOS process for passive RFID tags[J].半导体学报（英文版）,2013,34(8):94-98,5.

基金项目

Project supported by the National Key Technology Research and Development Program of the Ministry of Science and Technology of China (No.2012BAH20B02),the National High Technology Research and Development Program of China (No.2012AA012301),and the National Science and Technology Major Projects of the Ministry of Science and Technology of China (No.2012ZX03004007-002). （No.2012BAH20B02）

半导体学报（英文版）

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ISSN：1674-4926

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