华中科技大学学报（自然科学版）2013，Vol.41Issue(7)：67-70,102,5.
一种(50,32)BCH码高速并行编译码器设计
High-speed parallel codec design for (50,32)BCH Codes
摘要
Abstract
The coding and decoding process were studied to improve BCH (bose-claudhuri-hocquenghem) codec hardware and reduce time-consuming.Aimed at space environment,(50,32) BCH short ened codes was selected to meet double error correcting four error detecting of the 32 bit data.A greedy algorithm for solving shared expressions was introduced.By using the proposed algorithm,the circuits of the BCH encoder and computing syndromes have minimum area.By using direct decoding algorithm to calculate the error location polynomial,and removing the complex division operation,the efficiency of the decoder was improved.Using SMIC (semiconductor manufacturing international corporation) 130 nm standard CMOS (complementary metal oxide semiconductor) process to synthesized,results show that the critical path delay of the encoder is 1.10 ns,and that of the decoder is only 4.91 ns.关键词
译码器/纠错码/缩短码/BCH码/单粒子翻转/纠二检四Key words
decoder/ error-correcting codes/ shortened codes/ BCH codes/ single event upset/ double error correcting four error detecting分类
信息技术与安全科学引用本文复制引用
崔媛媛,张洵颖,沈绪榜,李伟..一种(50,32)BCH码高速并行编译码器设计[J].华中科技大学学报（自然科学版）,2013,41(7):67-70,102,5.基金项目
航天科技集团预研项目(2011AA120201). （2011AA120201）
