S 波段低相噪捷变频频率综合器设计OA
Design of a S-band, Low Phase Noise and Frequency Agility Frequency Synthesizer
介绍了一种S波段低相噪捷变频频率综合器设计方法.由于采用DDS+PLL的方式使此频率综合器相噪优于-115dBc/Hz@1kHz,跳频时间小于5us.
The design of a S-band frequency synthesizer with low noise and frequency agility is introduced. For the synthesizer attributed to the use of DDS+PLL, the phase noise is superior to -115dBc/Hz@1kHz and frequency change time is under 5us.
徐珏亮;费霞
上海航天 804所 上海 201109上海航天 804所 上海 201109
信息技术与安全科学
雷达频率综合器低相噪捷变频DDSPLL
radarfrequency synthesizerlow phase noisefrequency agilityDDSPLL
《数字技术与应用》 2012 (11)
138-139,2
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