电子器件2013，Vol.36Issue(4)：580-584,5.DOI:10.3969/j.issn.1005-9490.2013.04.034
基于FPGA的16 bit CRC校验查表法设计
Design of Look-up Table with 16 bit CRC Verification Base on FPGA
季鹏辉 1孟丁 2任勇峰3
作者信息
- 1. 中北大学仪器科学与动态测试教育部重点实验室
- 2. 电子测试技术国家重点实验室,太原030051
- 3. 北京第二炮兵驻699厂军事代表室,北京100076
- 折叠
摘要
Abstract
Look-up table design to achieve 16 bit CRC for serial communication process used in the CRC,adopted IP core of the Xilinx ISE 10.1 and established RAM,is used to deposit the 16 bit CRC verification I-type table in the CRC.The VHDL language is used to complete the implementation of the 16 bit CRC verification look-up table method.Based on the ChipScope Pro Analyzer of Xilinx company,online logical analysis verifies the feasibility of the design,and the design to be realized in practical applications,shows its good stability and accuracy.关键词
串行通信/循环冗余校验/查表法/现场可编程门阵列/IP核Key words
serial communication/ CRC (Cyclic Redundancy Check)/look-up table method/Field Programmable Gate Array (FPGA)/IP core分类
信息技术与安全科学引用本文复制引用
季鹏辉,孟丁,任勇峰..基于FPGA的16 bit CRC校验查表法设计[J].电子器件,2013,36(4):580-584,5.
