计算机技术与发展2013，Vol.23Issue(7)：183-186,4.DOI:10.3969/j.issn.1673-629X.2013.07.047
基于UVM实现时间同步电路的功能验证
Function Verification of Time Synchronization Circuit Based on UVM
摘要
Abstract
Time synchronization circuit module that is one important IP core of a developing network communication SoC chip provides precise time synchronization between the communication network subsystems,and therefore their correct functional verification has great significance.Using the traditional directional test method on its validation will be difficult to traverse all cases,and constrained random test,based-coverage driven UVM method,can reduce the test stimulus development,effective exhaustion to verify the function point.Introduce the verification platform process of design and implementation based on UVM verification methodology,through simulation and the coverage rate of the statistical analysis,prove that the method can effectively check the design defects,reduces verification time.关键词
UVM/覆盖率/寄存器模型Key words
UVM/coverage rate/register model分类
信息技术与安全科学引用本文复制引用
王世中,田泽,吴晓成,张荣华,王治,王纯委..基于UVM实现时间同步电路的功能验证[J].计算机技术与发展,2013,23(7):183-186,4.基金项目
"十二五"微电子预研(51308010601) （51308010601）
国防预研基金(9140A08010712HK6101) （9140A08010712HK6101）
中国航空工业集团公司创新基金(2010BD63111) （2010BD63111）
