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Design of a delay-locked-loop-based time-to-digital converter

Ma Zhaoxin Bai Xuefei Huang Lu

半导体学报（英文版）2013，Vol.34Issue(9)：105-111,7.

半导体学报（英文版）2013，Vol.34Issue(9)：105-111,7.DOI:10.1088/1674-4926/34/9/095003

Design of a delay-locked-loop-based time-to-digital converter

Ma Zhaoxin ¹Bai Xuefei ¹Huang Lu²

作者信息

1. Department of Electronic Science and Technology, University of Science and Technology of China, Hefei 230027, China
2. Experimental Center for Information Sciences, University of Science and Technology of China, Hefei 230027, China
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摘要

关键词

TDC/ DLL/ multiphase clock/ false lock/ jitter

Key words

TDC/ DLL/ multiphase clock/ false lock/ jitter

引用本文复制引用

Ma Zhaoxin,Bai Xuefei,Huang Lu..Design of a delay-locked-loop-based time-to-digital converter[J].半导体学报（英文版）,2013,34(9):105-111,7.

基金项目

Project supported by the National Science and Technology Major Project (No.2011ZX03004-002-01) and the Fundamental Research Funds for the Central Universities (No.WK2100230012). （No.2011ZX03004-002-01）

半导体学报（英文版）

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ISSN：1674-4926

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