A new circuit for at-speed scan SoC testing

Lin Wei Shi Wenlong

半导体学报（英文版）2013，Vol.34Issue(12)：126-130,5.

半导体学报（英文版）2013，Vol.34Issue(12)：126-130,5.DOI:10.1088/1674-4926/34/12/125012

Lin Wei ¹Shi Wenlong¹

作者信息

1. Fujian Key Laboratory of Microelectronics & Integrated Circuits, College of Physics & Information Engineering of Fuzhou University, Fuzhou 350002, China
折叠

at-speed scan test/ on-chip clock/ transition-delay faults/ phase-locked loop

at-speed scan test/ on-chip clock/ transition-delay faults/ phase-locked loop

Lin Wei,Shi Wenlong..A new circuit for at-speed scan SoC testing[J].半导体学报（英文版）,2013,34(12):126-130,5.

Project supported by the Key Project Science and Technology Cooperation of Fujian Province,China (No.2013I0003). （No.2013I0003）

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ISSN：1674-4926

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