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A 4 GHz CMOS multiplier for sigma-delta modulated signals

Guo Xiaodan Meng Qiao Liang Yong

半导体学报（英文版）2014，Vol.35Issue(1)：91-95,5.

半导体学报（英文版）2014，Vol.35Issue(1)：91-95,5.DOI:10.1088/1674-4926/35/1/015003

Guo Xiaodan ¹Meng Qiao ²Liang Yong¹

作者信息

1. Institute of RF-& OE-ICs, Southeast University, Nanjing 210096, China
2. Engineering Research Center of RF-ICs & RF-Systems, Ministry of Education, Nanjing 210096, China
折叠

CMOS/ sigma-delta modulation/ multiplier/ bit-stream

CMOS/ sigma-delta modulation/ multiplier/ bit-stream

Guo Xiaodan,Meng Qiao,Liang Yong..A 4 GHz CMOS multiplier for sigma-delta modulated signals[J].半导体学报（英文版）,2014,35(1):91-95,5.

Project supported by the National Natural Science Foundation of China (No.60576028). （No.60576028）

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ISSN：1674-4926

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