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Impedance matching for the reduction of signal reflection in high speed multilevel three-dimensional integrated chips

Liu Xiaoxian Zhu Zhangming Yang Yintang Wang Fengjuan Ding Ruixue

半导体学报（英文版）2014，Vol.35Issue(1)：121-128,8.

半导体学报（英文版）2014，Vol.35Issue(1)：121-128,8.DOI:10.1088/1674-4926/35/1/015008

Impedance matching for the reduction of signal reflection in high speed multilevel three-dimensional integrated chips

Liu Xiaoxian ¹Zhu Zhangming ¹Yang Yintang ¹Wang Fengjuan ¹Ding Ruixue¹

作者信息

1. School of Microelectronics, Xidian University, Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices, Xi'an 710071, China
折叠

摘要

关键词

3D integration/ TSV/ signal reflection/ impedance matching/ S-parameter

Key words

3D integration/ TSV/ signal reflection/ impedance matching/ S-parameter

引用本文复制引用

Liu Xiaoxian,Zhu Zhangming,Yang Yintang,Wang Fengjuan,Ding Ruixue..Impedance matching for the reduction of signal reflection in high speed multilevel three-dimensional integrated chips[J].半导体学报（英文版）,2014,35(1):121-128,8.

基金项目

Project supported by the National Natural Science Foundation of China (No.61204044). （No.61204044）

半导体学报（英文版）

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ISSN：1674-4926

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