计算机工程与应用Issue(3)：181-184,4.DOI:10.3778/j.issn.1002-8331.1304-0257
全数字锁相环实现的自适应低通滤波电路
Adaptive low pass filter circuit implemented by ADPLL
摘要
Abstract
This paper presents the structure and implementation of an adaptive low-pass filter system based on ADPLL (All Digital Phase Locked Loop). The input signal is converted into square signal after shaping. The square signal is phase-locked and transformed into synchronous frequency multiplication signal after passing through the ADPLL based on FPGA. The frequency multiplication signal is input into switched-capacitor filter MAX295 as clk which can control corner frequency. The cutoff frequency of the low-pass filter is tracked automatically with the change of signal frequency. The design principle is introduced. The design method of ADPLL and phase-locked frequency multiplier based on FPGA is analyzed in detail. The experiment results illustrate that the system is feasible and effective. The system is able to realize the self-tracking of double-frequency and filtering when the frequency varies from 1 kHz to 50 kHz.关键词
现场可编程门阵列(FPGA)/全数字锁相环/自适应/开关电容滤波/低通滤波器Key words
Field-Programmable Gate Array(FPGA)/All Digital Phase Locked Loop(ADPLL)/adaptive/switched-capacitor filter/low pass filter分类
信息技术与安全科学引用本文复制引用
马胜前,杨阳,刘娟芳..全数字锁相环实现的自适应低通滤波电路[J].计算机工程与应用,2014,(3):181-184,4.基金项目
国家自然科学基金（No.61162017，No.20927004）；甘肃省教育厅资助项目（No.1101-03）。 （）
