计算机科学与探索Issue(4)：385-396,12.DOI:10.3778/j.issn.1673-9418.1309012
核分组的多核处理器优化方法
Grouping Cores for Chip Multiprocessors Optimization
摘要
Abstract
In chip multiprocessors (CMP), as the number of cores increases, the average distance between the requestors and the home nodes becomes longer, and certain hot nodes are incurred by the unbalanced accesses to the different banks of the distributed share cache. These cases lead to the higher average latency of L1 cache misses. To conquer this problem, this paper divides the cores into groups of 2×2 nodes, and introduces the neighboring data prober (NDP). By deciding if a miss can be served by the L1 cache of a neighbor node, NDP can leverage the node-level spatial locality of the data accesses of parallel programs. Also, this paper optimizes the coherence protocol for the new architecture. The evaluation results illustrate that the proposed cache optimization improves the performance, lowers the network traffic and saves energy.关键词
多核处理器/高速缓存/片上网络Key words
chip multiprocessors/cache/network on chip分类
信息技术与安全科学引用本文复制引用
李国红,汪东升,刘振宇,李崇民,刘根贤,郭三川..核分组的多核处理器优化方法[J].计算机科学与探索,2014,(4):385-396,12.基金项目
The National Natural Science Foundation of China under Grant No.60833004(国家自然科学基金), the National High Technology Research and Development Program of China under Grant No.2012AA010905(国家高技术研究发展计划(863计划)) （国家自然科学基金）
the Cross Discipline Foundation of Tsinghua National Laboratory for Information Science and Technology (清华大学信息科学与技术国家实验室交叉学科基金) （清华大学信息科学与技术国家实验室交叉学科基金）
