无线电工程Issue(2)：17-20,4.
基于FPGA的QC-LDPC码分层译码器设计
Design on QC-LDPC Layered Decoder Based on FPGA
摘要
Abstract
Because the non-layered QC-LDPC codes which constructed through circle-cancellmethod can't use partly parallel structure,a new layered-decoding structure based on FPGA is proposed in this paper.The simulation results show that the performance of the improved decoding algorithm is better,compared with the traditional layered decoding algorithm. The design for 2048 code length, 3/4 code rate,(3,12) non-layered QC-LDPC codes can be completed under Strtix II EP2S60F484C3 FPGA of Altera,Inc.When the clock frequency is 90 MHz and the maximum iteration number is 5,the decoding throughput can be up to 93.85 Mbps.关键词
QC-LDPC码/抑制短环构造/不可分层/FPGAKey words
QC-LDPC codes/circle-cancellmethod/non-layered/FPGA分类
信息技术与安全科学引用本文复制引用
彭阳阳,仰枫帆..基于FPGA的QC-LDPC码分层译码器设计[J].无线电工程,2014,(2):17-20,4.基金项目
航空科学基金资助项目（20105552）。 （）
