微型机与应用Issue(3)：24-26,30,4.
基于FPGA和单片机的守时系统设计
Design of the time keeping system based on FPGA and SCM
曾一凡 1吴思琪1
作者信息
- 1. 沈阳工业大学 信息科学与工程学院，辽宁 沈阳 110870
- 折叠
摘要
Abstract
The current situation and the important role of the time keeping system is described. Combined with the actual situation of power network, the paper analyses some questions which has been met in the development of the time keeping system and designs a time keeping system by GPS or Beidou as time mark . The double constant temperature trough crystal oscillator MV180 is used as the input clock of system, and uses SCM to control DAC7512 to adjust its frequency. Firstly, the system carries on the frequency division processing to the adjusted local clock signal. Then compares with the standard second signal received by the GPS or Beidou, adjusts the phase of the signal through frequency division by using FPGA and SCM. Finally, it outputs the standard second pulse, thus obtains the high accuracy time base quickly. It also can maintain the signal invariably after GPS or Beidou lock-lose to achieve the time synchronization.关键词
GPS 时标/守时系统/相位调整/D/A 转换/时间同步/电力系统Key words
GPS time mark/time keeping system/phase modulation/D/A transformation/time synchronization/power system分类
电子信息工程引用本文复制引用
曾一凡,吴思琪..基于FPGA和单片机的守时系统设计[J].微型机与应用,2014,(3):24-26,30,4.
