现代电子技术Issue(5)：80-82,3.
一种基于FPGA的流水线8051 IP核的设计与实现
Design and implementation of pipe-line 8051 IP core based on FPGA
摘要
Abstract
A design scheme of IP Core of 8051MCU based on FPGA is proposed,which is compatible with standard 8051MCU in instruction. Using decoding - perform two pipeline stages structure,it passed through the simulation and synthesis. The theoretical speed has 6 to 10 times increasing than traditional 8051MCU. For the complexity of CISC pipeline design,an effi-cient realization is proposed,which can make the execution structure operating nearly in full state. The three kinds of conflicts which traditional pipeline must face to is solved simply and effectively. The design is described by Verilog HDL,and verified with ModelsimSE 6.2 simulator. Finally the code is downloaded into Xilinx FPGA chip to make physical test. The results of LED light water experiment show that the core achieves the expected goal.关键词
8051微处理器/流水线/FPGA/控制冒险Key words
5018MCU/Verilog HDL/pipeline/FPGA/control hazards分类
信息技术与安全科学引用本文复制引用
王发栋,杜慧玲,史翔..一种基于FPGA的流水线8051 IP核的设计与实现[J].现代电子技术,2014,(5):80-82,3.基金项目
国家自然科学基金项目（51072162）；陕西省国际合作项目 （）
