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A14-bit 50 MS/s sample-and-hold circuit for pipelined ADC

Yue Sen Zhao Yiqiang Pang Ruilong Sheng Yun

半导体学报（英文版）2014，Vol.35Issue(5)：118-123,6.
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半导体学报（英文版）2014，Vol.35Issue(5)：118-123,6.DOI:10.1088/1674-4926/35/5/055009

A14-bit 50 MS/s sample-and-hold circuit for pipelined ADC

A14-bit 50 MS/s sample-and-hold circuit for pipelined ADC

Yue Sen 1Zhao Yiqiang 1Pang Ruilong 1Sheng Yun1

作者信息

  • 1. School of Electronic Information Engineering, Tianjin University, Tianjin 300072, China
  • 折叠

摘要

关键词

sample/hold circuit/ pipeline ADC/ gain-boosted OTA/ bootstrapped switch

Key words

sample/hold circuit/ pipeline ADC/ gain-boosted OTA/ bootstrapped switch

引用本文复制引用

Yue Sen,Zhao Yiqiang,Pang Ruilong,Sheng Yun..A14-bit 50 MS/s sample-and-hold circuit for pipelined ADC[J].半导体学报（英文版）,2014,35(5):118-123,6.

基金项目

Project supported by the National Science and Technology Major Project of China (No.2012ZX03004008). （No.2012ZX03004008）

半导体学报（英文版）

OACSCDCSTPCDEI

1674-4926

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