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A 14-bit 100-MS/s 85.2-dB SFDR pipelined ADC without calibration

Zhao Nan Luo Hua Wei Qi Yang Huazhong

半导体学报（英文版）2014，Vol.35Issue(7)：149-154,6.

半导体学报（英文版）2014，Vol.35Issue(7)：149-154,6.DOI:10.1088/1674-4926/35/7/075006

A 14-bit 100-MS/s 85.2-dB SFDR pipelined ADC without calibration

Zhao Nan ¹Luo Hua ¹Wei Qi ¹Yang Huazhong¹

作者信息

1. Division of Circuits and Systems, Department of Electronic Engineering, Tsinghua University, Beijing 10084, China
折叠

摘要

关键词

analog-to-digital converter/ADC/pipeline/calibration-free/timing/clock buffer

Key words

analog-to-digital converter/ADC/pipeline/calibration-free/timing/clock buffer

引用本文复制引用

Zhao Nan,Luo Hua,Wei Qi,Yang Huazhong..A 14-bit 100-MS/s 85.2-dB SFDR pipelined ADC without calibration[J].半导体学报（英文版）,2014,35(7):149-154,6.

基金项目

Project supported by the National Science Foundation for Young Scientists of China (No.61306029) and the National High Technology Research and Development Program of China (No.2013AA014103). （No.61306029）

半导体学报（英文版）

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ISSN：1674-4926

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