首页|期刊导航|半导体学报（英文版）|A 2 GS/s 8-bit folding and interpolating ADC in 90 nm CMOS

A 2 GS/s 8-bit folding and interpolating ADC in 90 nm CMOS

He Wenwei Meng Qiao Zhang Yi Tang Kai

半导体学报（英文版）2014，Vol.35Issue(8)：140-144,5.

半导体学报（英文版）2014，Vol.35Issue(8)：140-144,5.DOI:10.1088/1674-4926/35/8/085004

A 2 GS/s 8-bit folding and interpolating ADC in 90 nm CMOS

He Wenwei ¹Meng Qiao ²Zhang Yi ³Tang Kai³

作者信息

1. Institute of RF-& OE-ICs, Southeast University, Nanjing 210096, China
2. School of Information Science and Technology, Lu Dong University, Yantai 264100, China
3. Institute of RF-& OE-ICs, Southeast University, Nanjing 210096, China
折叠

摘要

关键词

folding and interpolating/ SHA/ comparator/ foreground digital calibration circuit

Key words

folding and interpolating/ SHA/ comparator/ foreground digital calibration circuit

引用本文复制引用

He Wenwei,Meng Qiao,Zhang Yi,Tang Kai..A 2 GS/s 8-bit folding and interpolating ADC in 90 nm CMOS[J].半导体学报（英文版）,2014,35(8):140-144,5.

基金项目

Project supported by National Basic Research Program of China (No.2010CB327400) and the Natural Science Foundation of Shandong Province,China (No.ZR2013FL007). （No.2010CB327400）

半导体学报（英文版）

OACSCDCSTPCDEI

ISSN：1674-4926

访问量0

下载量0

段落导航