首页|期刊导航|半导体学报（英文版）|An 11-bit 22-MS/s 0.6 mW SAR ADC with parasitic capacitance compensation

An 11-bit 22-MS/s 0.6 mW SAR ADC with parasitic capacitance compensation

Gu Weiru Ye Fan Ren Junyan

半导体学报（英文版）2014，Vol.35Issue(8)：151-157,7.

半导体学报（英文版）2014，Vol.35Issue(8)：151-157,7.DOI:10.1088/1674-4926/35/8/085006

An 11-bit 22-MS/s 0.6 mW SAR ADC with parasitic capacitance compensation

Gu Weiru ¹Ye Fan ¹Ren Junyan²

作者信息

1. State Key Laboratory of ASIC & System, Shanghai 201203, China
2. State Key Laboratory of ASIC & System, Shanghai 201203, China
折叠

摘要

关键词

analog-to-digital converter/ dynamic circuits/ parasitic capacitor compensation/ successive approximation register

Key words

analog-to-digital converter/ dynamic circuits/ parasitic capacitor compensation/ successive approximation register

引用本文复制引用

Gu Weiru,Ye Fan,Ren Junyan..An 11-bit 22-MS/s 0.6 mW SAR ADC with parasitic capacitance compensation[J].半导体学报（英文版）,2014,35(8):151-157,7.

基金项目

Project sponsored by the Natural Science Foundation of China (No.61006025),the Special Research Funds for Doctoral Program of Higher Education of China (No.20100071110026),and the National Science & Technology Major Project of China (No.2012ZX03001020-003). （No.61006025）

半导体学报（英文版）

OACSCDCSTPCDEI

ISSN：1674-4926

访问量0

下载量0

段落导航