半导体学报（英文版）2014，Vol.35Issue(9)：97-103,7.DOI:10.1088/1674-4926/35/9/095001
Performance analysis of a complete adiabatic logic system driven by the proposed power clock generator
Performance analysis of a complete adiabatic logic system driven by the proposed power clock generator
Jitendra Kanungo 1S.Dasgupta2
作者信息
- 1. Department of Electronics & Communication Engineering, Jaypee University of Engineering & Technology, Guna-473226,India
- 2. Microelectronics & VLSI Group, Department of Electronics & Communication Engineering Indian Institute of Technology, Roorkee-247667, India
- 折叠
摘要
关键词
clock-generator/energy recovery logic/low power/single phase sinusoidal clockKey words
clock-generator/energy recovery logic/low power/single phase sinusoidal clock引用本文复制引用
Jitendra Kanungo,S.Dasgupta..Performance analysis of a complete adiabatic logic system driven by the proposed power clock generator[J].半导体学报（英文版）,2014,35(9):97-103,7.
