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首页|期刊导航|半导体学报(英文版)|A simulation-based proposed high-k heterostructure AlGaAs/Si junctionless n-type tunnel FET

A simulation-based proposed high-k heterostructure AlGaAs/Si junctionless n-type tunnel FET

Shiromani Balmukund Rahi Bahniman Ghosh Pranav Asthana

半导体学报(英文版)2014,Vol.35Issue(11):59-63,5.
半导体学报(英文版)2014,Vol.35Issue(11):59-63,5.DOI:10.1088/1674-4926/35/11/114005

A simulation-based proposed high-k heterostructure AlGaAs/Si junctionless n-type tunnel FET

A simulation-based proposed high-k heterostructure AlGaAs/Si junctionless n-type tunnel FET

Shiromani Balmukund Rahi 1Bahniman Ghosh 2Pranav Asthana1

作者信息

  • 1. Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur 208016, India
  • 2. Microelectronics Research Center, 10100, Burnet Road, Bldg.160, University of Texas at Austin, Austin, TX, 78758, USA
  • 折叠

摘要

关键词

band-to-band tunneling (BTBT)/ TFET/ heterostructure junctionless tunnel field effect transistor (HJL-TFET)/ ION/IOFF ratio subthreshold slope/ VLSI

Key words

band-to-band tunneling (BTBT)/ TFET/ heterostructure junctionless tunnel field effect transistor (HJL-TFET)/ ION/IOFF ratio subthreshold slope/ VLSI

引用本文复制引用

Shiromani Balmukund Rahi,Bahniman Ghosh,Pranav Asthana..A simulation-based proposed high-k heterostructure AlGaAs/Si junctionless n-type tunnel FET[J].半导体学报(英文版),2014,35(11):59-63,5.

半导体学报(英文版)

OACSCDCSTPCDEI

1674-4926

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