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An analog front end with a 12-bit 3.2-MS/s SAR ADC for a power line communication system

Chen Huabin Xiang Jixuan Xue Xiangyan Chen Chixiao Ye Fan Xu Jun Ren Junyan

半导体学报(英文版)2014,Vol.35Issue(11):141-148,8.
半导体学报(英文版)2014,Vol.35Issue(11):141-148,8.DOI:10.1088/1674-4926/35/11/115008

An analog front end with a 12-bit 3.2-MS/s SAR ADC for a power line communication system

An analog front end with a 12-bit 3.2-MS/s SAR ADC for a power line communication system

Chen Huabin 1Xiang Jixuan 1Xue Xiangyan 1Chen Chixiao 1Ye Fan 1Xu Jun 1Ren Junyan1

作者信息

  • 1. State-Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China
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摘要

关键词

analog front end/ successive approximation register/ A/D/ power line communication

Key words

analog front end/ successive approximation register/ A/D/ power line communication

引用本文复制引用

Chen Huabin,Xiang Jixuan,Xue Xiangyan,Chen Chixiao,Ye Fan,Xu Jun,Ren Junyan..An analog front end with a 12-bit 3.2-MS/s SAR ADC for a power line communication system[J].半导体学报(英文版),2014,35(11):141-148,8.

半导体学报(英文版)

OACSCDCSTPCDEI

1674-4926

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