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A 0.8-4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications

Zhao Yuanxin Gao Yuanpei Li Wei Li Ning Ren Junyan

半导体学报（英文版）2015，Vol.36Issue(1)：125-139,15.

半导体学报（英文版）2015，Vol.36Issue(1)：125-139,15.DOI:10.1088/1674-4926/36/1/015001

A 0.8-4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications

Zhao Yuanxin ¹Gao Yuanpei ¹Li Wei ¹Li Ning ¹Ren Junyan¹

作者信息

1. State Key Laboratory of ASIC & System, Fudan University, Shanghai 201203, China
折叠

摘要

关键词

fractional-N frequency synthesizer/ all-digital phase-locked loop/ phase noise/ reference spur/ CMOS

Key words

fractional-N frequency synthesizer/ all-digital phase-locked loop/ phase noise/ reference spur/ CMOS

引用本文复制引用

Zhao Yuanxin,Gao Yuanpei,Li Wei,Li Ning,Ren Junyan..A 0.8-4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications[J].半导体学报（英文版）,2015,36(1):125-139,15.

基金项目

Project supported by the National Natural Science Foundation of China (No.61176029) and the National Twelve-Five Project (No.513***). （No.61176029）

半导体学报（英文版）

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ISSN：1674-4926

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