首页|期刊导航|半导体学报（英文版）|A low power, low noise figure quadrature demodulator for a 60 GHz receiver in 65-nm CMOS technology
半导体学报（英文版）2015，Vol.36Issue(4)：122-130,9.DOI:10.1088/1674-4926/36/4/045005
A low power, low noise figure quadrature demodulator for a 60 GHz receiver in 65-nm CMOS technology
A low power, low noise figure quadrature demodulator for a 60 GHz receiver in 65-nm CMOS technology
摘要
关键词
low power/low NF/CMOS/quadrature demodulator/frequency dividerKey words
low power/low NF/CMOS/quadrature demodulator/frequency divider引用本文复制引用
Najam Muhammad Amin,Wang Zhigong,Li Zhiqun,Li Qin,Liu Yang..A low power, low noise figure quadrature demodulator for a 60 GHz receiver in 65-nm CMOS technology[J].半导体学报（英文版）,2015,36(4):122-130,9.基金项目
Project supported by the National High Technology Research and Development Program of China (No.2011AA010200). （No.2011AA010200）
