电子科技大学学报Issue(5)：669-673,5.DOI:10.3969/j.issn.1001-0548.2014.05.006
SAR ADC中一种比较器失调和噪声容忍的模型
Low Power Offset and Noise Tolerant Model for Comparators of SAR ADC
摘要
Abstract
A lower power digital correction model for comparator offset and noise tolerance of successive approximation register (SAR) analog-to-digital converter (ADC) is presented. A fine comparator with smaller offset and noise has penalty of higher power and lower speed. This model involves a faster coarse comparator with less power in the first (n-m-1) cycles to relax those penalties. The errors of the coarse comparator are tolerated by the fine comparator through the redundant comparison cycle and the capacitor at (m+2) cycle. This model is able to tolerate noise and offset errors up to ±2mleast significant bit (LSB). A prototype of 10 bit 100 MS/s SAR ADC with this model is simulated in a 0.13μmCMOS technology. The post-simulation results of the prototype layout witnessed an effective number of bits (ENOB) of 9.27 bit are achieved at 100 MS/s with a power consumption of 2.01 mW under 1.2 V supply, resulting in a figure of merit (FoM) of 33 fJ/conv.关键词
低功耗电子/噪声容忍/失调容忍/逐次逼近型模数转换器Key words
low power electronics/noise tolerant/offset tolerant/SAR ADC分类
信息技术与安全科学引用本文复制引用
高俊枫,李梁,李广军,李强,郭志勇..SAR ADC中一种比较器失调和噪声容忍的模型[J].电子科技大学学报,2014,(5):669-673,5.基金项目
国家自然科学基金(61006027)；国家自然科学基金面上项目(61176025)；新世纪优秀人材计划(NCET-10-0297) （61006027）
