电子器件Issue(3)：435-440,6.DOI:10.3969/j.issn.1005-9490.2014.03.013
一种快速模乘运算器的设计
Design of a Fast Modular Multiplier
摘要
Abstract
A 257 bit fast modular multiplier is designed. Booth32 algorithm and Wallace CSA architecture are used to solve the problem of multiplication of large number consumed too long times. Our multiplier is three-level pipeline structure,the addition and subtraction algorithms are incorporated to the third multiplication. The simulation results indicate:the clock frequency of the chip is 140 MHz,the time of set up pipelining is 42. 329 ns,afterwards,every module multiplication required 7. 022 ns. Compared with the other modular multiplier,this design has higher per-formance. The module Multiplier designed in this paper can be used to the high performance operation of module multiplication,especially in the design of multi-core computing module.关键词
Montgomery模乘/大数乘法器/有限状态机/流水线技术Key words
Montgomery algorithm/multiplier/FSM/pipelining分类
信息技术与安全科学引用本文复制引用
曹军,刘兴辉,张文婧,赵宏亮,姜长仁..一种快速模乘运算器的设计[J].电子器件,2014,(3):435-440,6.基金项目
国家自然科学基金项目(21171081) （21171081）
辽宁省科技厅自然科学基金项目(20082050) （20082050）
辽宁省教育厅高等学校科研基金项目(L2010152) （L2010152）
