电子器件Issue(3)：646-649,4.DOI:10.3969/j.issn.1005-9490.2015.03.035
一种3.3 V低电源电压的1553 B总线收发器设计∗
Design of a 3.3 V Low Supply Voltage 1553B Bus Transceiver
摘要
Abstract
A system structure of bus transceiver based on 1553B bus is presented,and a 3.3 V low supply voltage 1553B bus transceiver which dynamic power dissipation is decreased effectively is designed. The simulation and test results show that all the transmitting and receiving function of this bus transceiver are realized with 3. 3 V supply voltage. The maximum dynamic power dissipation of 100% duty transmitter cycle is 0.5 W,which declines 1.7 W compared to the 5 V supply voltage 1553B bus transceiver. The chip is fabricated at 0.5 μm DPTM BCD(15 V) CMOS processes,and is adopted in low supply voltage 1553B bus product.关键词
收发器/低功耗/低压供电/1553B总线Key words
transceiver/low power dissipation/low voltage supply/1553B bus分类
信息技术与安全科学引用本文复制引用
印琴,于宗光,魏敬和,胡水根..一种3.3 V低电源电压的1553 B总线收发器设计∗[J].电子器件,2015,(3):646-649,4.基金项目
江苏省333工程科研项目( BRA2011115) （ BRA2011115）
