电子器件Issue(3)：650-654,5.DOI:10.3969/j.issn.1005-9490.2015.03.036
基于DDR2 SDRAM乒乓双缓冲的高速数据收发系统设计
High-Speed Data Transceiver System Based on DDR2 SDRAM Ping-Pong Double Buffering
摘要
Abstract
In the high-speed data transceiver system design, the first problem to be solved is the real-time data cache,However,the limited memory resources of FPGA can not meet the requirements of massive data cache,To solve the problem of system cache huge amounts of data,the system proposed ping-pong double buffering innovative design based on the DDR2 SDRAM. Design of two-way high-capacity asynchronous FIFO based on DDR2 SDRAM, selection logic operations to achieve a ping-pong between the two paths through the FPGA to achieve the cached da-ta . Experimental results show that the Data transceiver system based on DDR2 SDRAM realized every road 512 Mbit cache space and 200 MHz of the bus rate and solved the problem of the huge amounts of data cache.关键词
高速数据收发/乒乓双缓冲/DDR2 SDRAM技术/异步FIFOKey words
high-speed data transceiver system/ping-pong double buffering/DDR2 SDRAM Technology/asyn-chronous FIFO分类
信息技术与安全科学引用本文复制引用
刘杰,赛景波..基于DDR2 SDRAM乒乓双缓冲的高速数据收发系统设计[J].电子器件,2015,(3):650-654,5.
