电子器件Issue(4)：754-758,5.DOI:10.3969/j.issn.1005-9490.2015.04.008
一种数模混合SoC的系统级后仿真验证平台∗
A System-Level Post-Simulation Verification Platform for Mixed-Signal SoC
摘要
Abstract
Regarding the problem of slow post-simulation speed of the large-scale mixed-signal System-on-Chip ( SoC ) , a system-level post-simulation verification platform for mixed-signal SoC is proposed. Based on the traditional Verilog-cdl post-simulation verification platform and popular EDA tools,the proposed platform utilizes a Verilog-cdl-Verilog simulation method in which the modules with long simulation time are replaced by the Verilog ones. As a result,the verification process is obviously fastened. The design flow of the simulation platform is de-scribed in details,including the verification environment setup,the system script design and the mixed-signal simu-lation interface design. The instruction set simulation based on the verification platform is tested and verified. The results indicate that the verification platform is feasible and reliable, which can shorten the developing period of large-scale mixed-signal SoC.关键词
数模混合系统芯片/后仿真/Verilog-cdl-Verilog/验证平台Key words
mixed signal SoC/post-simulation/Verilog-cdl-Verilog/verification platform分类
信息技术与安全科学引用本文复制引用
胡小刚,赵琳娜,虞致国,魏敬和,顾晓峰..一种数模混合SoC的系统级后仿真验证平台∗[J].电子器件,2015,(4):754-758,5.基金项目
江苏省自然科学基金项目( BK20130156) （ BK20130156）
中央高校基本科研业务费专项资金项目( JUSRP1026,JUSRP51323B) （ JUSRP1026,JUSRP51323B）
江苏省科技厅产学研联合创新资金项目( BY2013015-19) （ BY2013015-19）
江苏省六大人才高峰项目( DZXX-027) （ DZXX-027）
江苏省普通高校研究生实践创新计划项目( SJZZ_0148) （ SJZZ_0148）
