桂林电子科技大学学报Issue(2)：91-95,5.
一种IEEE 802.11 n流水线FFT/IFFT的实现
Implementation of an IEEE 802.1 1n pipeline FFT/IFFT
摘要
Abstract
In order to simplify the complicity of the wireless communication system,a kind of FFT/IFFT processor is de-signed based on the SISO-OFDM system in IEEE 802.11n.Because the SISO-OFDM system needs 64 and 128 points fast Fourier transform,the FFT processor employs radix-4/2 mixed algorithm and single-path delay feedback architecture.The optimized butterfly unit is designed in the hardware.The simplified storage of twiddle factors and an optimized output RAM are also used to minimize the chip area.The 10 bit processor is designed in UMC 110 nm CMOS process,the chip area is a-bout 0.3 mm2 .Compared to the traditional memory based on FFT,the hardware cost and the power consumption are de-creased largely.关键词
快速傅里叶变换/单路延迟反馈结构/蝶形运算单元/流水线结构Key words
fast Fourier transformation/single-path delay feedback/butterfly operation unit/pipeline architecture分类
信息技术与安全科学引用本文复制引用
石钦,林基明,周立国,李彩俊..一种IEEE 802.11 n流水线FFT/IFFT的实现[J].桂林电子科技大学学报,2014,(2):91-95,5.基金项目
国家自然科学基金(61261017) （61261017）
广西自然科学基金(2013GXNSFAA019334) （2013GXNSFAA019334）
