光通信研究Issue(1)：35-38,4.DOI:10.13756/j.gtxyj.2015.01.012
用于光收发模块的I2C总线极限测试控制器
I2 C bus limit test controller for optical transceiver modules
摘要
Abstract
This paper designs an I2 C bus limit test controller for assessing the robustness of the I2 C bus communication of opti-cal transceiver modules.In this design,the parameters exceed the limits by a certain range according to the I2 C communication protocol.This controller is designed on CPLD using Verilog HDL,which is used to perform two main functions,I2 C frequency test and bus line characteristics test.Software simulation and hardware implementation verify the correctness of this design. This controller can also conduct tests of other kinds of I2 C slave devices with the only need to change device address,offset ad-dress and other relevant parameters.关键词
I2C总线/极限测试/Verilog硬件描述语言/复杂可编程逻辑器件Key words
I2 C bus/limit test/Verilog HDL/CPLD分类
信息技术与安全科学引用本文复制引用
柯昆,杨奇..用于光收发模块的I2C总线极限测试控制器[J].光通信研究,2015,(1):35-38,4.
