哈尔滨工程大学学报2015，Vol.36Issue(7)：943-948,6.DOI:10.3969/j.issn.1006-7043.201403029
面向802.11ac的安全加速引擎Gbps VLSI架构设计与实现
Design and implementation of Gbps VLSI architecture of the cipher engine orienting to IEEE 802.11ac
摘要
Abstract
In this paper, the implementation of multiple security protocols for IEEE 802.11i was researched. A very large scale integration ( VLSI) architecture of the multi-mode cipher engine supporting WEP/TKIP/CCMP proto-cols was presented taking into account the demand for high throughput of the next generation wireless local area net-work ( WLAN) system that is represented by IEEE 802.11ac. A key searching algorithm based on Hash scheme was proposed to reduce the lookup clock latency. For the high throughput hardware implementation of advanced encryp-tion standard ( AES) algorithm, composite field arithmetic was employed. In order to improve the data throughput and reduce the response time, dual AES computing core with parallel structure was used to implement the cipher block chaining message authentication code ( CCM) mode. The proposed design was implemented in both FPGA and ASIC. The results show that the cipher engine with reconfiguration architecture can achieve 33 clock cycles, and the computing throughput is 3.747 Gbit/s when the work frequency is 322 MHz.关键词
安全加速引擎/多模式/密钥查找/哈希算法/AES算法/响应延迟/吞吐率Key words
cipher engine/multi-mode/key searching/Hash scheme/AES algorithm/response time/throughput分类
信息技术与安全科学引用本文复制引用
潘志鹏,吴斌,尉志伟,叶甜春..面向802.11ac的安全加速引擎Gbps VLSI架构设计与实现[J].哈尔滨工程大学学报,2015,36(7):943-948,6.基金项目
国家重大科技专项资助项目(2012ZX03004004). （2012ZX03004004）
