湖南大学学报（自然科学版）Issue(10)：91-95,5.
小数分频频率合成器中Σ-Δ调制器设计与实现
Design and Implementation ofΣ-ΔModulator in Fractional-N Frequency Synthesizer
摘要
Abstract
This paper presented a design and implementation study of a three-order all-digital MASHΣ-Δmodulator,which can be used in Fractional-N Frequency Synthesizer applications.To achieve the de-sired operation frequency while providing low-power dissipation and small area,the pipelining technique was utilized in the design.The circuit was described by using the Verilog hardware description language, and the operating frequency of the modulator is 240.56 MHz based on QuartusⅡ.Eventually,the SMIC 0.18μm CMOS process was adopted,and the circuit layout was completed.The chip's area is 34148.5μm2 ,and the total power of the chip is 1.28 mW.Compared with traditional design,it can result in a 31. 23% area reduction and 46.14% power reduction.关键词
调制器/频率合成器/MASH1-1-1/流水线技术/CMOSKey words
modulator/frequency synthesizer/MASH/pipelining technique/CMOS分类
信息技术与安全科学引用本文复制引用
晏敏,徐欢,乔树山,杨红官,郑乾,戴荣新,程呈..小数分频频率合成器中Σ-Δ调制器设计与实现[J].湖南大学学报（自然科学版）,2014,(10):91-95,5.基金项目
湖南省科技计划资助项目(2012GK3151) （2012GK3151）
