摘要
Abstract
Direct Digital Waveform Synthesis(DDWS), which can ensure the greatest degree of signal details are not missed, is a main method to generate irregular waveform. Though existing memory structure in DDWS is able to overcome the contradiction between high-speed quality and memory space, the number of sampling must be multiples of the number of channel, which restricts the signal accuracy. To solve this problem, a method of memory structure is proposed. Though the study of the principle in the waveform output sequence, adaptive selection of parallel output data is implemented by modifying the address generators, adaptive sorting of parallel output data is implemented by adding parallel re-constructor. Through simulation and verification on Field Programmable Gate Array(FPGA), the results indicate that the restriction on the number of sampling is overcome and output accuracy of the signal is improved. By analyzing the resource dissipation, the overhead increment of logic resources is less than 1%of total logic resources in FPGA, which has a significant advantage on the hardware resources.关键词
直接数字波形合成/存储结构/自适应/并行重构器/现场可编程门阵列/综合后仿真/输出精度Key words
Direct Digital Waveform Synthesis(DDWS)/storage structure/adaptive/parallel re-constructor/Field Programmable Gate Array(FPGA)/post syntheses simulation/output accuracy分类
信息技术与安全科学
