计算机工程Issue(7)：272-276,5.DOI:10.3969/j.issn.1000-3428.2014.07.056
可重构浮点混合/连续乘-加器的设计与实现
Design and Implementation of Reconfigurable Floating-point Fused/Continuous Multiply-adder
摘要
Abstract
As floating-point continuous multiply-add, fused multiply-add and multiply and three-operands addition operations are used more and more frequently in the field of scientific computing, a multi-purpose floating-point unit is designed which supports floating-point continuous multiply-add, fused multiply-add and multiply and three-operands addition is an urgent need. In this situation, a reconfigurable floating-point fused/continuous multiply-add structure is proposed. This reconfigurable floating-point fused/continuous multiply-adder can achieve a variety of floating-point data manipulation through configuration of the control bit. This reconfigurable floating-point fused/continuous multiply-adder uses eight-stage pipe-line. It can achieve single-cycle multiply-accumulate, which greatly improves the throughput of the data processing and supports three-operand addition and two-operand sum’s accumulate simultaneously. This design is simulated and verified in Modelsim SE6.6f’s environment and the function is correct. When this design is implemented on Xilinx Virtex-6 FPGA, the resource consumption is 2 631 LUTs and the frequency is up to 250 MHz, and the result proves that the reconfigurable floating-point fused/continuous multiply-adder has a large value in use.关键词
浮点/连续乘-加/混合乘-加/三操作数加/可重构/流水线Key words
floating point/continuous multiply-add/fused multiply-add/three-operands addition/reconfigurable/pipeline分类
信息技术与安全科学引用本文复制引用
洪琪,何敏,范继聪,袁粲..可重构浮点混合/连续乘-加器的设计与实现[J].计算机工程,2014,(7):272-276,5.基金项目
国家“863”计划基金资助项目(2009AA012201)；专用集成电路与系统国家重点实验室开放基金资助项目(12KF004)。 （2009AA012201）
