计算机工程与应用Issue(19)：78-84,7.DOI:10.3778/j.issn.1002-8331.1311-0018
基于资源复用的RSA加速器层次化架构
Hierarchical architecture of RSA accelerator based on hardware resource reuse
赵开兰 1张晓旭 1马德 2黄凯 1严晓浪1
作者信息
- 1. 浙江大学 电气工程学院，杭州 310027
- 2. 杭州电子科技大学 微电子CAD所，杭州 310018
- 折叠
摘要
Abstract
To improve the performance of the RSA cryptography system for the application of modular frequent change, a novel hierarchical architecture of RSA accelerator is proposed. With hardware resource reuse with Montgomery Modular Multiplier, both modular inverse and R2 mod M arithmetic function are supported by the proposed accelerator to improve performance of RSA key generation and Montgomery Modular multiplication. As the experiment shows, compared with previous works, the performance of RSA accelerator is 2 times faster for the application of modular frequent change under 14% resource overhead. What’s more, the accelerator achieves one order of magnitude performance increasing for R2 mod M calculation comparing with the method of reusing Modular Exponentiation module.关键词
RSA加密算法/加速/层次化设计/资源复用Key words
RSA encryption algorithm/accelerate/hierarchical design/resource reuse分类
信息技术与安全科学引用本文复制引用
赵开兰,张晓旭,马德,黄凯,严晓浪..基于资源复用的RSA加速器层次化架构[J].计算机工程与应用,2014,(19):78-84,7.
