计算机工程与应用Issue(23)：61-64,4.DOI:10.3778/j.issn.1002-8331.1312-0173
5.8 GHz 0.18μmCMOS低噪声放大器的设计
Design of 58 GHz 018 μm CMOS low noise amplifier Computer Engineering and Applications, 2014, 50(23):61-64
摘要
Abstract
Based on TSMC 0.18μm CMOS technology, a novel circuit topology for a CMOS Low-Noise-Amplifier(LNA) is presented in this paper. In this circuit, a cascode topology with inter-stage matching network is designed at the frequency of 5.8 GHz. Choosing a inter-stage matching network presents lower power dissipation while achieving reasonable power gain. In order to save the chip area, a LC network is used instead of the large inductor. The simulation results show the for-ward gain(S21)is about 10.3 dB, as well as less than-16 dB isolation(S12)while operating at 5.8 GHz. The input imped-ance(S11)and the output impedance(S22)also represent good performance. In addition, the minimum noise figure and sig-nal linearity performance are quite good. It consumes only 12.7 mW under a 1.5 V voltage supply.关键词
低噪声放大器/CMOS/噪声系数/线性度Key words
low noise amplifier/CMOS/noise figure/linearity分类
信息技术与安全科学引用本文复制引用
周洪敏,张瑛,丁可柯..5.8 GHz 0.18μmCMOS低噪声放大器的设计[J].计算机工程与应用,2014,(23):61-64,4.基金项目
国家自然科学基金青年科学基金（No.61106021）；江苏省高校自然科学基金（No.11KJB510019）；南京邮电大学青蓝工程基金（No.NY210037）。 （）
