计算机工程与应用Issue(3)：45-49,60,6.DOI:10.3778/j.issn.1002-8331.1304-0110
二维椭圆硬件加速算法研究及其FPGA实现
Research on ellipse hardware accelerating algorithm and its FPGA imple-mentation
摘要
Abstract
To make up for the loss or lack of ellipse accelerating function in embedded systems of 2D graphics acceleration, a design of an ellipse hardware accelerating unit is proposed. The unit supports complete function of ellipse drawing and filling. Using the top-down design method, the overall architecture of the unit is defined and divided into different function modules according to functional requirements. Pipelines are adopted to control operations among modules and decompose the graphics into horizontal line segments to output. Proper algorithms applicable for hardware implementation in this design are proposed and converted to logic designs using Verilog HDL. After simulation completed, the design is synthesized and implemented on FPGA. Simulation and debug results show that all the algorithms used are feasible, and the ellipse accel-erating unit can correctly and quickly complete ellipse drawing and filling with various parameters configuration combina-tions. It’s proved that this design can well satisfy the requirements of embedded 2D graphics acceleration systems.关键词
二维图形/椭圆/填充/现场可编程门阵列(FPGA)Key words
2D-graphic/ellipse/fill/Field-Programmable Gate Array(FPGA)分类
信息技术与安全科学引用本文复制引用
谢周标,周毅,龙斌..二维椭圆硬件加速算法研究及其FPGA实现[J].计算机工程与应用,2015,(3):45-49,60,6.基金项目
国家重点基础研究发展规划（973）（No.2007CB310500）。 （）
