计算机工程与应用Issue(8)：32-36,5.DOI:10.3778/j.issn.1002-8331.1405-0335
卷积神经网络的FPGA并行加速方案设计
FPGA-based design for convolution neural network
摘要
Abstract
According to the characteristics of the Convolution Neural Network(CNN), a FPGA-based acceleration pro-gram which uses deep-pipeline architecture is proposed for the MNIST data set. In this program, theoretically 28 × 28 clock cycles can finish the whole calculation and get the output of the CNN. For the propagation stage of the training pro-cess, and in the same network structure and the same data set, this FPGA program with 50 MHz frequency can achieve nearly five times speedup compared to GPU version(Caffe), achieve eight times speedup compared to 12 CPU cores. While the FPGA program just costs 26.7%power which GPU version costs.关键词
卷积神经网络/现场可编程门阵列(FPGA)/深度流水/加速Key words
convolution neural network/Field Programmable Gate Array(FPGA)/deep-pipeline/acceleration分类
信息技术与安全科学引用本文复制引用
方睿,刘加贺,薛志辉,杨广文..卷积神经网络的FPGA并行加速方案设计[J].计算机工程与应用,2015,(8):32-36,5.基金项目
国家高技术研究发展计划（863）（No.2010AA012302，No.2013AA01A208）；国家自然科学基金（No.61040048，No.61303003， No.41374113）。 （）
