计算机工程与应用Issue(10)：84-88,5.DOI:10.3778/j.issn.1002-8331.1306-0084
适用于CCSDS的“一帧一密”加/解密方案的FPGA实现
WANG Zhenyu, et al. FPGA implementation of“One Frame One Key”encryption/decryption solution suitable for CCSDS
摘要
Abstract
Encryption plays an important role in satellite data transmission systems, especially satellite and ground data transmission. It realizes an encryption/decryption solution for CCSDS. The system is designed based on Xilinx Spartan6 FPGA, AES encryption algorithm and the CTR operation mode. The design is able to realize data encryption less than block size without generating redundant data, overcome the limitation of the block encryption algorithm to encrypt the fixed block size data. The paper puts forward the encryption scheme of“one frame one key”to improve the security of the algorithm. Pipeline and logical multiplex are used in the system to improve speed and save chip resources. Under the clock frequency of 33 MHz, encryption and decryption speed are up to 264 Mb/s.关键词
高级加密标准(AES)/计算器模式/一帧一密/加/解密/现场可编程门阵列Key words
Advanced Encryption Standard(AES)/Counter(CTR)/one frame one key/encryption/decryption/Field Pro-grammable Gate Array(FPGA)分类
信息技术与安全科学引用本文复制引用
刘兰,姚行中,王振宇,杨晓非..适用于CCSDS的“一帧一密”加/解密方案的FPGA实现[J].计算机工程与应用,2015,(10):84-88,5.基金项目
第二炮兵预先研究基金（No.EP121007）。 （）
