计算机技术与发展Issue(10)：97-100,4.DOI:10.3969/j.issn.1673-629X.2014.10.023
一种RapidIO IP核的设计与验证
Design and Implementation of a RapidIO IP Core
摘要
Abstract
The RapidIO bus as one of the representatives of the third generation bus,is the best choice of the interconnection between pro-cessors. But in the domestic,the study of RapidIO bus is just begun,and the RapidIO IP is bought from outland mostly. Based on the Ra-pidIO V1. 3 protocol,describe a design and implementation method for the RapidIO bus,and has carried on the comprehensive test in vir-tual platform and FPGA platform. The simulation result shows that,this design meets the RapidIO V1. 3 protocol,and is simple to imple-ment,has good reusability,and can be easily used in the design of FPGA and chip as RapidIO interface.关键词
RapidIO/IP核设计/验证方法Key words
RapidIO/IP core design/verification method分类
信息技术与安全科学引用本文复制引用
蔡叶芳,田泽,李攀,何嘉文..一种RapidIO IP核的设计与验证[J].计算机技术与发展,2014,(10):97-100,4.基金项目
“十二五”微电子预研(51308010601) （51308010601）
总装2012预研基金(9140A08010712HK61095) （9140A08010712HK61095）
中国航空工业集团公司创新基金(2010BD63111) （2010BD63111）
