计算机技术与发展Issue(6)：163-165,175,4.DOI:10.3969/j.issn.1673-629X.2015.06.036
一种低抖动带宽自适应锁相环的设计与实现
Design and Implementation of an Adaptive Bandwidth PLL with Wide Temperature Range and Low Jitter
摘要
Abstract
With the development of high speed communication system and the improvement of the transmission speed,PLL to be the core circuit of providing precision clock is not only required to produce low jitter and low noise clock,but also demanded wide frequency range and multi-protocol support,but the fixed bandwidth PLL cannot reach the requirement of multi-protocol. An adaptive bandwidth PLL with wide temperature range and low jitter is designed for achieving the requirements of multi-protocol in the unify configuration,using the comparator and charge pump to form a feedback loop to flexibly change the charge pump current,and making the loop bandwidth a-daptively adjusted at different rates. Adopt the improved duty-cycle controller,voltage control oscillator and charge pump circuit to de-crease the noise of PLL. This chip is fabricated in 0. 13 μm CMOS process. The measured results show that the output frequency is from 1. 062 5 to 3 GHz and the data rate covers 1. 062 5~5. 9 Gbps,RJ is less than 1. 3 ps,the operating temperature range is-55~125 ℃, which meet the protocol requirements of FC-PI-4、PCIE1. 1 and Rapid IO1. 3,and has been successfully applied to a variety of high speed SerDes chip.关键词
锁相环/带宽自适应/宽温/低抖动Key words
PLL/adaptive bandwidth/wide temperature range/low jitter分类
信息技术与安全科学引用本文复制引用
刘颖,田泽,邵刚,刘敏侠..一种低抖动带宽自适应锁相环的设计与实现[J].计算机技术与发展,2015,(6):163-165,175,4.基金项目
“十二五”微电子预研(51308010601,51308010711) （51308010601,51308010711）
总装预研基金(9140A08010712HK6101) （9140A08010712HK6101）
