计算机技术与发展Issue(7)：217-220,4.DOI:10.3969/j.issn.1673-629X.2015.07.049
一种高速SERDES抖动容限的高效仿真验证方法
A Highly Efficient Simulation Verification Method for High Speed SERDES Jitter Tolerance
摘要
Abstract
Aiming at high speed SERDES bus validation at the receiving end,put forward a jitter tolerance verification method,effectively reducing the risk of a flow chip. For many factor can affect SERDES,such as temperature,wiring and the parasitic of channel,it needs to work stably in many cases,the assessment of jitter characteristics for the receiving circuit in design phase is a complex validation process, with few reports. Based on the protocol of PCIE,SRIO and FC,a fast and efficient verification and evaluation method is proposed for RX end jitter tolerance. The model proposed in this method can accurately assess the convenient characteristics of RX. The test result indicates that the jitter tolerance evaluated by the model can tally with the test results accurately,significantly optimizing the performance of RX in design stage and reducing the risk of flow chip largely.关键词
SERDES/抖动容限/验证/CDR/时钟恢复电路Key words
SERDES/jitter tolerance/verification/CDR/clock recovery circuit分类
信息技术与安全科学引用本文复制引用
邵刚,田泽,李世杰,吕俊盛..一种高速SERDES抖动容限的高效仿真验证方法[J].计算机技术与发展,2015,(7):217-220,4.基金项目
“十二五"微电子预研(51308010601,51308010711) （51308010601,51308010711）
总装预研基金(9140A08010712HK6101) （9140A08010712HK6101）
