无线电工程Issue(3)：30-33,4.DOI:10.3969/j.issn.1003-3106.2015.03.09
基于FPGA的DVB-S2 LDPC编码器的设计与实现
Design of LDPC Encoder in DVB-S2 Based on FPGA
摘要
Abstract
Due to their excellent bit⁃error⁃rate performance,Low Density Parity Check ( LDPC) codes have been adopted by the second Digital Video Satellite Broadcast Standard (DVB⁃S2).In order to meet the application requirement of broadband multimedia sat⁃ellite system,this paper develops a technique using RAM storage element on FPGA chip to store the check bits of LDPC codes and a kind of encoder structure of LDPC employed by DVB⁃S2.The architecture explores the periodic structure of the adopted codes by per⁃forming on the flypartial⁃parallel computation of the parity check bits. The design has been implemented with both serial and parallel input on a EP3C120F484I7 Cyclone Ⅲ Atera FPGA.The throughput is tested in 2.6 Gb/s successfully.关键词
DVB-S2标准/LDPC编码器/宽带多媒体卫星系统/FPGAKey words
DVB-S2 standard/LDPC encoder/broadband multimedia satellite system/FPGA分类
信息技术与安全科学引用本文复制引用
王延鹏,潘申富,杨宏伟..基于FPGA的DVB-S2 LDPC编码器的设计与实现[J].无线电工程,2015,(3):30-33,4.基金项目
国家部委基金资助项目。 （）
