无线电工程Issue(7)：24-26,3.DOI:10.3969/j.issn.1003-3106.2015.07.07
FPGA高速并行m序列的设计
Design of FPGA High-speed Paralleling m Sequence
李荷 1赵贤明 1郝志松1
作者信息
- 1. 中国电子科技集团公司第五十四研究所，河北 石家庄050081
- 折叠
摘要
Abstract
To resolve the problem of processing clock frequency far below data generation rate in generating high⁃speed m sequence in FPGA,this paper adopts three methods of delay method,equivalent method and substitution method to design the parallel structure for generating paralleling m sequence and implements it on FPGA. The test results show that the generated paralleling m sequences fully meet the standard format requirements.This parallel structure achieves better application effects in the tests of scrambling and descrambling,BER,and coding and decoding in high⁃speed communication system.关键词
PN序列/并行结构/高速通信Key words
PN sequence/parallel structure/high-speed communication分类
信息技术与安全科学引用本文复制引用
李荷,赵贤明,郝志松..FPGA高速并行m序列的设计[J].无线电工程,2015,(7):24-26,3.
