微型机与应用Issue(24)：2-4,3.
基于AES的可重构加密系统的FPGA设计
FPGA design of reconfigurable encryption system based on AES
摘要
Abstract
In accordance with the deficiency of traditional software encryption methods in terms of speed and resource consumption, the paper proposes a hardware design program based on AES (Advanced Encryption Standard). The program adopts the currently-popular EDA technology, achieves a reconfigurable encryption system on FPGA chip, and uses hardware description language, to achieve a series of functions in encryption algorithm, such as shift, S cartridge replacement functions, and linear feedback shifting register. Design input, model synthesis, placement and routing, functional simulation were all accomplished on Altera′s Quartus II development platform. Besides, the downloaded files were tested by the FPGA chip of Cyclone series. The experimental result shows that the system has unique physical security and high speed.关键词
信息安全/高级加密标准/现场可编程门阵列/Quartus IIKey words
information security/AES/FPGA/Quartus II分类
信息技术与安全科学引用本文复制引用
杨斐,彭鹏..基于AES的可重构加密系统的FPGA设计[J].微型机与应用,2014,(24):2-4,3.基金项目
湖北省教育厅科学技术研究项目 （）
