西安电子科技大学学报（自然科学版）Issue(6)：57-64,8.DOI:10.3969/j.issn.1001-2400.2014.06.010
一种具有延迟校准功能的可编程多相位时钟电路
Programmable mlti-phase clock circuit with delay calibration
摘要
Abstract
Based on the principle of the delay-locked loop (DLL),this paper introduces a programmable multi-phase clock circuit with a delay calibration loop.The proposed circuit offers a clock signal with a precision of 390 ps and optimum timing for a variety of CCD signal processors.One cycle of the main clock is divided into 32 parts equally,while timing with a tunable duty cycle is generated by the programmable phase combiner.The increase in delay elements worsens the delay time error between different phases of the output signals,and hence a delay time calibration loop is applied to suppress this effect.In SMIC 0.1 8μm 3.3 V CMOS process,with a 80 MHz main clock,the post simulation results show that the proposed circuit generates an output clock with a 2%~98% duty cycle,a 1.14 ps edge to edge jitter and a less than 5 ps calibrated delay time error.关键词
电荷耦合器件/延迟锁相环/延迟校准环路/可编程相位组合器Key words
charge couple device/delay locked loop/delay calibration loop/programmable phase分类
信息技术与安全科学引用本文复制引用
刘术彬,朱樟明,赵扬,恩云飞,刘帘曦,杨银堂..一种具有延迟校准功能的可编程多相位时钟电路[J].西安电子科技大学学报（自然科学版）,2014,(6):57-64,8.基金项目
国家自然科学基金资助项目(61234002,61322405,61306044,61376033) （61234002,61322405,61306044,61376033）
国家863计划资助项目(2012AA012302,2013AA014103) （2012AA012302,2013AA014103）
教育部博士点基金资助项目(20120203110017) （20120203110017）
电子元器件可靠性物理及其应用技术重点实验室开放基金资助项目(ZHD201101) （ZHD201101）
